Inter-Integrated Circuit (I2C) is a multi-master single-ended two-wire communication interface configured to transmit or receive information serially from an I2C master device to an I2C slave device using a bus including a serial data line (SDA) and a serial clock line (SCL). I2C master devices can include a microcontroller (μC) or other electronic device configured to issue a clock and address slave devices and I2C slave devices can include peripheral devices, such as an analog-to-digital controller (ADC), a digital-to-analog controller (DAC), or one or more other peripheral devices configured to receive a clock and address.
FIG. 1 illustrates generally an example Inter-Integrated Circuit (I2C) system 100 including an I2C master device 105, an I2C slave device 110, and pull-up resistors 111, 112 configured to pull a serial data line (SDA) and a serial clock line (SCL) of a bus, respectively, to a source voltage (VDD).
FIG. 2 illustrates generally an example Inter-Integrated Circuit (I2C) transaction sequence 200 including a start bit 115, initialization bits 116, data bits 117, and a stop bit 118 on clock and data lines (SCL, SDA, respectively). Start and stop bits 115, 118 are unique signals that can be generated by an I2C master device, and are defined as rising or falling edges on the serial data line (SDA) while the serial clock line (SCL) is kept high, as illustrated in the transaction sequence 200.
An I2C master device can send a start bit 115 (e.g., a falling edge on SDA as SCL is kept high) on a two-wire bus that can be received by an I2C slave device. Reception of the start bit 115 by an I2C slave device can reset the I2C slave device internal bus logic. After sending the start bit 115, the I2C master device can send initialization bits 116, including an address sequence, and can wait for an acknowledge from an I2C slave device having a matching internal address sequence. If the address sequence is acknowledged, the I2C master device can send or read data bits 117 and wait for an acknowledge (ACK) from the I2C slave. The I2C master device can complete the data transfer by generating a stop bit 118 (e.g., a rising edge on SDA as SCL is kept high). In an example, each device on an I2C system can have a unique address (e.g., an I2C slave ID), enabling several devices (e.g., I2C slave devices, etc.) to coexist on the same two-wire bus using the different addresses.
For some devices, the unique address can be defined using one or more pins. For example, using traditional addressing techniques, two unique addresses can be selected using a single pin, four unique addresses can be selected using two pins, etc. However, in certain examples, multiple I2C chips of the same type can be used in a single application (e.g., two or more of the same type of digital-to-analog converters, two or more of the same type of analog-to-digital converters, etc.). If the existing I2C system requires more than two unique addresses, one pin may not be enough to separate the address space. One solution is to increase the number of address pins on the I2C device. However, increasing the number of pins on an integrated circuit (IC) can be expensive (e.g., increasing the size of the chip, the size of the package, the test time, etc.). Alternatively, ICs can be produced with mask programmable IDs or one-time programmable (OTP) IDs. However, these solutions can increase the cost of production, including marketing, logistics, testing, production, etc. Other solutions include a fixed internal address setting, which can eliminate the need for dedicated address pins. However, in the case of an address collision, the fixed internal address setting may not be changed.